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Tools

TeLLA Deepali Koppad
TeLLA stands for TEsting of Low Latency Asynchronous circuits.
TeLLA is a tool for testing circuits obtained by direct mapping. TeLLA reads in a verilog netlist and generates a set of test vectors required to test the circuit. The verilog netlist must be obtained using the OptiMist tool available at [http://async.org.uk/besst/optimist/ ]. Using the -t (testing) option in OptiMist a netlist including the test features can be obtained.
TeLLa provides a table consisting of a list of test vectors, it also consists information on the time required to apply one test vector to the circuit, total number of test vectors and the total time to apply all the test vectors.
[ http://async.org.uk/stella/tella/ ].
ProtoDe Danil Sokolov
ProtoDe is a software tool for protocol decomposition of Signal Transition Graphs (STGs).
[ http://async.org.uk/stella/protode/ ].
LESTA Agnes Madalinski
LESTA stands for Logical-Effort-based Static Timing Analysis - "lesta" also is the female adjective for "quick" in Italian.
LESTA is a tool which, given an STG and its relative Verilog netlist, outputs the delay information for each input-to-output path of the STG. These delays are calculated using the Logical Effort method.
Alternatively the tool can calculate dthe delay information using characterised delay information. The tool requires a library file which contains the Logical Effort and characterised information for all the gates present in the Verilog netlist.
[ http://async.org.uk/stella/lesta/ ].
Indie Danil Sokolov
Indie is a software tool which computes the smallest fully indicating implementation of a circuit.
[ http://async.org.uk/screen/indie/ ].
ConfRes Agnes Madalinski
Interactive Coding Conflict Resolver based on Core Visualisation The tool supports manual resolution of coding conflicts in asynchronous circuit specification given as Signal Transition Graphs (STGs) and displays them as partial orders (finite and complete prefixes of STG unfoldings). The manual approach although efficient requires a significant effort from the designer. The tool ConfRes assists the designer by visualising the conflict cores, their superposition and the constraints on signal insertion.
[ http://async.org.uk/besst/confres/ ].
OptiMist Danil Sokolov
OptiMist (Optimise and Map) is a package of tools that optimise Signal Transition Graph specifications and map them into asynchronous circuits.
[ http://async.org.uk/besst/optimist/ ].
PN2DCs Delong Shang
Petri nets to David Cell Hardware Circuit.
[ http://async.org.uk/besst/pn2dcs/ ].
Verimap Danil Sokolov
VeriMap is a design kit for converting a single-rail RTL netlists into a dual-rail circuits resistant to DPA attacks.
[ http://async.org.uk/screen/verimap/ ].
VERISYN Frank Burns
Asynchronous High Level Synthesis Tool.
[ http://async.org.uk/besst/verisyn/ ].

Last modified 9/6/2006 by IGC