Workshop on Neural Engineering using Reconfigurable Hardware 2012
Call for Papers
Understanding of the human brain is one of the grand challenges of the 21st century due to the potential to develop new medical solutions and to create novel engineering applications. This has resulted in the emergence of a large and expanding research community focused upon neural engineering. By applying common engineering principles and techniques with neurally-inspired designs and algorithms we are able to learn about the processes within the brain or develop revolutionary applications, such as neuro-prosthetics with the capability to restore sensory, motor or even cognitive functionality.
The motivation provided by the potential results of furthering our understanding of the brain also drives research into next-generation hardware architectures and designs. For example, to develop large-scale models of the brain that demonstrate realistic functionality, and hence allow for simulation of the brain's processes, it is a requirement to improve the current state-of-the-art in computational platforms, in terms of performance, scalability and efficiency. The product of developing these large-scale models may in turn produce ideas and concepts for innovative design practices for engineering applications.
The rapidly evolving nature, high performance requirements and concurrent processes of neural models encourage the utilization of FPGAs in neural engineering. As such, FPGAs have been shown to be used for neural networks, bio-physically accurate iono-neuromorphic models, and hybrid bio-silicon systems.
Therefore, the aim of this workshop is to bring together researchers working on neural engineering who utilize FPGAs, with the goal of providing an opportunity to discuss new ideas, present solutions to neural challenges and to develop proposals for future work. The topics of interest could include:
- Neurally-inspired designs and algorithms
- Tools for neural applications including large-scale neural networks
- Results and analysis of neural models
- Spike sorting techniques and methods
- Reconfigurable designs for neural simulation platforms
- Models of synaptic plasticity
- Brain-machine interfaces and neuro-prosthetics
- Hybrid bio-silicon networks
- Emerging technologies and design challenges
Submission
Alongside regular papers, we encourage the submission of short papers, reviews of the area and details of work in progress.
Short papers detailing works in progress and abstracts of work should be 2-4 pages long. Regular papers may be up to 8 pages in total.
Papers should be formatted as per the guidelines on the FPL2012 website.
Papers may be submitted via the online portal. Alternatively, you can email graeme.coapes@ncl.ac.uk with your submission or any question regarding the submission process.
All accepted papers will be published online at www.async.org.uk/nerh2012.
Key Dates
Submission Open: 25th June 2012Submission Deadline: 1st August 2012Notification of Acceptance: 6th August 2012FPL Conference Date: August 29-31st 2012Workshop Date: 1st September 2012
Information
The workshop is being held in conjunction with FPL2012 at the University of Oslo, Norway.
Schedule
Saturday 1st September 2012
- 1300 - Reconfigurable Computing in Hybrid Closed-Loop Systems - Jun Wen Luo, Graeme Coapes, Terrence Mak
- 1330 - Efficient Handling of Synaptic Updates in FPGA-based Large-Scale Neural Network Simulations - Paul J Fox, Simon W Moore
- 1400 - A Large-Scale Spiking Neural Network Accelerator for FPGA Systems - Kit Cheung, Simon R Schultz, Wayne Luk
Registration
If you would like to register for this workshop please email graeme.coapes@ncl.ac.uk
Contacts
Co-organizers:
Terrence Mak
terrence.mak@ncl.ac.uk
School of Electrical and Electronic Engineering, Newcastle University
Department of Computer Science and Engineering, The Chinese University of Hong Kong
Graeme Coapes
graeme.coapes@ncl.ac.uk
School of Electrical and Electronic Engineering, Newcastle University