#module = task1seq;
#scope: task1seq (2 signals, 0 logic)
tri unsigned input [8] a
reg unsigned output [8] z
#endscope task1seq
#scope: task1seq.Subseq2 (4 signals, 0 logic) task task1seq.Subseq2
#begin
#assign 
task1seq.Subseq2.y
-
task1seq.Subseq2.a
task1seq.Subseq2.b
#end 
#assign 
task1seq.Subseq2.z
-
task1seq.Subseq2.y
1
#end 
#end
reg unsigned input [8] a
reg unsigned input [8] b
reg unsigned [8] y
reg unsigned output [8] z
#endscope task1seq.Subseq2
#always
#begin
#begin
#assign 
task1seq.Subseq2.a
task1seq.a
#end 
#assign 
task1seq.Subseq2.b
6
#end 
#assign 
task1seq.z
task1seq.Subseq2.z
#end 
#end
#assign 
task1seq.z
+
task1seq.z
task1seq.a
#end 
#end
