//inputs & outputs
#module = whilesum;
#scope: whilesum (10 signals, 0 logic)
tri unsigned input [1] cw
reg unsigned [8] n
reg unsigned [8] s
reg unsigned [8] syn
reg unsigned [2] t
tri unsigned input [1] tst
tri unsigned input [1] tw
tri unsigned input [8] x
tri unsigned input [8] y
reg unsigned output [8] z
#endscope whilesum
