#module = seq;
#scope: seq (4 signals, 0 logic)
tri unsigned input [8] a
reg unsigned [8] x
reg unsigned [8] y
reg unsigned output [8] z
#endscope seq
#always
#begin
#assign 
seq.x
+
seq.a
6
#end 
#assign 
seq.y
+
seq.x
2
#end 
#assign_nb 
seq.z
+
seq.y
1
#end
