#module = seq;
#scope: seq (4 signals, 0 logic)
tri unsigned input [8] a
tri unsigned input [8] b
reg unsigned [8] x
reg unsigned output [8] y
#endscope seq
#always
#begin
#assign 
seq.x
seq.a
#end 
#assign 
seq.y
+
seq.x
1
#end 
#assign 
seq.x
seq.b
#end 
#assign_nb 
seq.y
+
seq.y
seq.x
#end
