#module = seq1;
#scope: seq1 (4 signals, 0 logic)
tri unsigned input [8] a
reg unsigned [8] x
reg unsigned [8] y
reg unsigned output [8] z
#endscope seq1
#always
#begin
#assign 
seq1.x
+
6
seq1.a
#end 
#assign 
seq1.y
+
seq1.x
seq1.a
#end 
#assign_nb 
seq1.z
+
seq1.y
seq1.a
#end
