#module = repeatloop;
#scope: repeatloop (4 signals, 0 logic)
reg unsigned [8] a
reg unsigned output [8] r
tri unsigned input [8] v
reg unsigned [8] x
#endscope repeatloop
#always
#begin
#assign 
repeatloop.a
1
#end 
#assign 
repeatloop.x
1
#end 
#assign
repeatloop.cnt1
1
#end
#while
#comp
e
100
repeatloop.cnt1
#assign 
repeatloop.x
+
repeatloop.x
1
#end 
#assign
repeatloop.cnt1
+
repeatloop.cnt1
1
#end
#endwhile
#assign_nb 
repeatloop.r
+
repeatloop.v
repeatloop.a
#end
