#module = cond;
#scope: cond (6 signals, 1 logic)
tri unsigned input [8] a
tri unsigned input [8] b
reg unsigned output [8] y
reg unsigned output [8] z
#endscope cond
#always
#if (...)
e
cond.a
0
#begin
#assign 
cond.y
1
#end 
#if (...)
e
cond.b
0
#assign 
cond.z
3
#end 
#else
#assign 
cond.z
4
#end 
#end
#else
#assign 
cond.y
2
#end 
