#module = seq;
#scope: seq (3 signals, 0 logic)
tri unsigned input [8] a
reg unsigned output [8] x
reg unsigned output [8] y
#endscope seq
#always
#fork
#begin
#assign 
seq.x
seq.a
#end 
#assign_nb 
seq.x
+
seq.x
1
#end
#begin
#assign 
seq.y
seq.a
#end 
#if (...)
e
seq.y
0
#assign 
seq.y
seq.x
#end 
#else
#assign 
seq.y
1
#end 
#end
#join
