//inputs & outputs
#module = Dec;
#scope: Dec (9 signals, 0 logic)
tri unsigned input [8] cw
reg unsigned output [8] ew
reg unsigned output [6] lw
reg unsigned [6] n
reg unsigned [8] s
reg unsigned [2] stat
reg unsigned output [2] sw
reg unsigned [32] syn
reg unsigned [2] t
#endscope Dec
