#module = cond;
#scope: cond (2 signals, 0 logic)
tri unsigned input [8] a
reg unsigned output [8] z
#endscope cond
#always
#case (...) <2 cases>
e
cond.a
0
1
#assign 
cond.z
2
#end 
2
#assign 
cond.z
3
#end 
#endcase
