#module = wloop;
#scope: wloop (5 signals, 0 logic)
reg unsigned [8] a
reg unsigned output [8] r
tri unsigned input [8] v
reg unsigned [8] vv
reg unsigned [8] x
#endscope wloop
#always
#begin
#assign 
wloop.a
1
#end 
#assign 
wloop.x
1
#end 
#assign 
wloop.vv
wloop.v
#end 
#while
#comp
G
100
wloop.x
#begin
#assign 
wloop.vv
*
wloop.vv
2
#end 
#assign 
wloop.x
+
wloop.x
1
#end 
#end
#endwhile
#assign_nb 
wloop.r
+
wloop.vv
wloop.a
#end
