module dr_ha (
   a_0,
   a_1,
   b_0,
   b_1,
   co_0,
   co_1,
   sum_0,
   sum_1
);

   input a_0;
   input a_1;
   input b_0;
   input b_1;
   output co_0;
   output co_1;
   output sum_0;
   output sum_1;
   wire n0;
   wire n1;
   wire n2;
   
   c2 I0 (n0, a_0, b_0);
   c2 I1 (n1, a_0, b_1);
   c2 I2 (n2, a_1, b_0);
   c2 I3 (co_1, a_1, b_1);
   OR2 I4 (n0, co_1, sum_0);
   OR2 I5 (n1, n2, sum_1);
   OR3 I6 (n0, n1, n3, co_0);
endmodule

