module dr_and2 (
   i0_0,
   i0_1,
   i1_0,
   i1_1,
   q_0,
   q_1
);

   input i0_0;
   input i0_1;
   input i1_0;
   input i1_1;
   output q_0;
   output q_1;
   wire n0;
   wire n1;
   wire n2;

   c2 I0 (q_1, i0_1, i1_1);
   c2 I1 (n2, i0_1, i1_0);
   c2 I2 (n1, i0_0, i1_1);
   c2 I3 (n0, i0_0, i1_0);
   OR3 I4 (n0, n1, n2, q_0);
endmodule

