module comp_dr_8 (
   x,
   xb,
   y,
   yb,
   req,
   gre,
   equ,
   les
);

   input [7:0] x;
   input [7:0] xb;
   input [7:0] y;
   input [7:0] yb;
   input req;
   output gre;
   output equ;
   output les;
   wire w1gre;
   wire w1equ;
   wire w1les;
   wire w0gre;
   wire w0equ;
   wire w0les;
   wire w1;
   wire w2;

   comp_dr_4 I0 (x[7:4], xb[7:4], y[7:4], yb[7:4], req, w1gre, w1equ, w1les);
   comp_dr_4 I1 (x[3:0], xb[3:0], y[3:0], yb[3:0], req, w0gre, w0equ, w0les);
   c2 I2 (equ, w1equ, w0equ);
   c2 I3 (w1, w1equ, w0gre);
   c2 I4 (w2, w1equ, w0les);
   OR2 I5 (w1gre, w1, gre);
   OR2 I6 (w1les, w2, les);
endmodule

