module comp_dr_4 (
   x,
   xb,
   y,
   yb,
   req,
   gre,
   equ,
   les
);

   input [3:0] x;
   input [3:0] xb;
   input [3:0] y;
   input [3:0] yb;
   input req;
   output gre;
   output equ;
   output les;
   wire w3gre;
   wire w3equ;
   wire w3les;
   wire w2gre;
   wire w2equ;
   wire w2les;
   wire w1gre;
   wire w1equ;
   wire w1les;
   wire w0gre;
   wire w0equ;
   wire w0les;
   wire w1;
   wire w2;
   wire w3;
   wire w4;
   wire w5;
   wire w6;
   wire w7;
   wire w8;
   wire w9;
   wire w10;

   comp_dr_1 I0 (x[3], xb[3], y[3], yb[3], req, w3gre, w3equ, w3les);
   comp_dr_1 I1 (x[2], xb[2], y[2], yb[2], req, w2gre, w2equ, w2les);
   comp_dr_1 I2 (x[1], xb[1], y[1], yb[1], req, w1gre, w1equ, w1les);
   comp_dr_1 I3 (x[0], xb[0], y[0], yb[0], req, w0gre, w0equ, w0les);
   c2 I4 (w1, w3equ, w2equ);
   c2 I5 (w2, w1equ, w0equ);
   c2 I6 (w3, w3equ, w2gre);
   c2 I7 (w4, w3equ, w2les);
   c2 I8 (w5, w1equ, w0gre);
   c2 I9 (w6, w1equ, w0les);
   c2 I10 (equ, w1, w2);
   c2 I11 (w7, w1, w5);
   c2 I12 (w8, w1, w6);
   c2 I13 (w9, w1, w1gre);
   c2 I14 (w10, w1, w1les);
   OR4 I15 (w3gre, w3, w9, w7, gre);
   OR4 I16 (w3les, w4, w10, w8, les);
endmodule



