module comp_dr_1 (
   x,
   xb,
   y,
   yb,
   req,
   gre,
   equ,
   les
);

   input x;
   input xb;
   input y;
   input yb;
   input req;
   output gre;
   output equ;
   output les;
   wire w1;
   wire w2;
   wire w3;
   wire w4;
   wire w5;
   wire w6;

   AND2 I0 (x, req, w1);
   AND2 I1 (xb, req, w2);
   AND2 I2 (y, req, w3);
   AND2 I3 (yb, req, w4);
   OR2 I4 (w1, w4, w5);
   OR2 I5 (w2, w3, w6);
   c2 I6 (gre, w1, w4);
   c2 I7 (equ, w5, w6);
   c2 I8 (les, w2, w3);
endmodule

