module SRsetreset_V (
   s,
   s_ack,
   r,
   r_ack,
   out
);

   input s;
   output s_ack;
   input r;
   output r_ack;
   output out;
   wire w1;

   NA2 I0 (s, w1, out);
   NA2 I1 (out, r, w1);
   OR2 I2 (s, w1, s_ack);
   OR2 I3 (r, out, r_ack);
endmodule

