Low Power Asynchronous Interlocked Pipelined CMOS (IPCMOS) Circuits Operating at 3.3 - 4.5 GHz

Stanley E. Schuster

IBM Research Centre, NY, USA

An asynchronous circuit technique suitable for multi - GHz operation using interlocked local clocks will be described. These circuits drive a path through a cross section of a typical 64b multiplier stage at 3.3 - 4.5 GHz in 0.18um 1.5V CMOS technology. Calculations show IPCMOS can achieve power reductions of 5X to 10X in pipelined stages. The circuits and techniques used to achieve high performance and low power will be presented.